Peer Review Friday

The team is finishing up a week of serious engineering with a thorough peer design review of principal engineer Jonny‘s 16-layer HDI PCB designed with Altium Designer and SolidWorks. At the center: a massive Xilinx, Inc. Zynq UltraScale+ MPSoC (FPGA fabric + 64-bit ARM SoC) part. Two banks of DDR4 2400 MT/s memory (from Micron[…]